Development of a dynamic code generator in C and Python, to reduce the energy consumption of high-performance ARM cores (Cortex-A8, Cortex-A9). Expertise in ARMv7-A assembly language, including FP and SIMD. Development of micro-architectural simulators (gem5/McPAT) for performance and power estimation.
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Nov 08, 2015 · Configure the FPGA, write a C program in Nios II IDE and download it to the board, and you should see everything working fine. One of my concerns was with the size of the on-chip memory size. So I decided it would be better to use the SDRAM on board to for the instructions and data instead of using the on-chip memory.
Architectural simulation – we will at this point configure the architectural simulator based on your application and data run GEM5 simulations. In cooperation we will within a few weeks know the compression and memory expansion that Ziptilion™ technology will achieve for your data and system architecture.